OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 172

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
172 BIST signals added. simont 7825d 10h /8051/trunk/rtl/verilog/
171 fix bug in DA operation. simont 7833d 07h /8051/trunk/rtl/verilog/
158 fix bug. simont 7837d 13h /8051/trunk/rtl/verilog/
153 `ifdef added. simont 7839d 07h /8051/trunk/rtl/verilog/
152 sub_result output added. simont 7839d 07h /8051/trunk/rtl/verilog/
151 remove pc_r register. simont 7839d 07h /8051/trunk/rtl/verilog/
150 fix some bugs. simont 7839d 07h /8051/trunk/rtl/verilog/
149 pipelined acces to axternal instruction interface added. simont 7839d 07h /8051/trunk/rtl/verilog/
148 include "8051_defines" added. simont 7839d 07h /8051/trunk/rtl/verilog/
146 fix bug in movc intruction. simont 7861d 07h /8051/trunk/rtl/verilog/
145 fix bug in case of sequence of inc dptr instrucitons. simont 7866d 11h /8051/trunk/rtl/verilog/
144 chsnge comp.des to des1 simont 7866d 11h /8051/trunk/rtl/verilog/
143 add wire sub_result, conect it to des_acc and des1. simont 7866d 11h /8051/trunk/rtl/verilog/
142 optimize state machine. simont 7867d 13h /8051/trunk/rtl/verilog/
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7867d 14h /8051/trunk/rtl/verilog/
140 cahnge assigment to pc_wait (remove istb_o) simont 7867d 14h /8051/trunk/rtl/verilog/
139 add aditional alu destination to solve critical path. simont 7868d 08h /8051/trunk/rtl/verilog/
138 Change buffering to save one clock per instruction. simont 7868d 08h /8051/trunk/rtl/verilog/
137 change to fit xrom. simont 7868d 13h /8051/trunk/rtl/verilog/
136 registering outputs. simont 7868d 13h /8051/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.