URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 23

Rev	Log message	Author	Age	Path
23	mul & div use 4 clocks	simont	8125d 08h	/8051/trunk/rtl/verilog/
22	fix some bugs	simont	8125d 08h	/8051/trunk/rtl/verilog/
21	mul bug fixed	markom	8125d 13h	/8051/trunk/rtl/verilog/
20	multiplier and divider changed so they complete in 4 cycles	markom	8125d 15h	/8051/trunk/rtl/verilog/
19	combinatorial loop removed	simont	8126d 08h	/8051/trunk/rtl/verilog/
17	fix some bugs	simont	8129d 13h	/8051/trunk/rtl/verilog/
16	inputs ram and op2 removed	simont	8129d 13h	/8051/trunk/rtl/verilog/
15	commbinatorial loop removed	simont	8129d 13h	/8051/trunk/rtl/verilog/
13	some bug fix	simont	8130d 11h	/8051/trunk/rtl/verilog/
12	des1_r in alu port list	simont	8130d 11h	/8051/trunk/rtl/verilog/
11	des2_r removed	simont	8130d 11h	/8051/trunk/rtl/verilog/
10	% replaced with ^ in uart; some minor improvements	markom	8130d 17h	/8051/trunk/rtl/verilog/
9	removed unused compare states	markom	8132d 10h	/8051/trunk/rtl/verilog/
8	some IDS optimizations	markom	8132d 10h	/8051/trunk/rtl/verilog/
7	immediate1 & immediate2 registers moved to oc8051_immediate_sel	markom	8132d 12h	/8051/trunk/rtl/verilog/
6	psw combinatorial loop removed	markom	8132d 14h	/8051/trunk/rtl/verilog/
5	more linter corrections; 2 tests still fail	markom	8132d 14h	/8051/trunk/rtl/verilog/
4	Code repaired to satisfy the linter; testbech fails	markom	8132d 16h	/8051/trunk/rtl/verilog/
2	Initial CVS import	simont	8148d 13h	/8051/trunk/rtl/verilog/