URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 46

Rev	Log message	Author	Age	Path
46	prepared header	simont	7939d 17h	/8051/trunk/rtl/verilog/
45	prepared header	simont	7939d 17h	/8051/trunk/rtl/verilog/
44	prepared header	simont	7939d 18h	/8051/trunk/rtl/verilog/
41	remove unused files	simont	7939d 19h	/8051/trunk/rtl/verilog/
40	added sigals for interacting with external ram	simont	7959d 21h	/8051/trunk/rtl/verilog/
38	fix some bugs	simont	7966d 19h	/8051/trunk/rtl/verilog/
37	added signals ack, stb and cyc	simont	7966d 19h	/8051/trunk/rtl/verilog/
36	fix bugs in mode 0	simont	7966d 19h	/8051/trunk/rtl/verilog/
32	overflow repaired	simont	7968d 00h	/8051/trunk/rtl/verilog/
31	fix some bugs	simont	7974d 16h	/8051/trunk/rtl/verilog/
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	7977d 22h	/8051/trunk/rtl/verilog/
29	fix some bugs	simont	7977d 23h	/8051/trunk/rtl/verilog/
28	remove syn signal	simont	7977d 23h	/8051/trunk/rtl/verilog/
27	fix some bugs	simont	7977d 23h	/8051/trunk/rtl/verilog/
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	7978d 01h	/8051/trunk/rtl/verilog/
25	divider and multiplier pass test	markom	7978d 20h	/8051/trunk/rtl/verilog/
23	mul & div use 4 clocks	simont	7979d 15h	/8051/trunk/rtl/verilog/
22	fix some bugs	simont	7979d 15h	/8051/trunk/rtl/verilog/
21	mul bug fixed	markom	7979d 20h	/8051/trunk/rtl/verilog/
20	multiplier and divider changed so they complete in 4 cycles	markom	7979d 23h	/8051/trunk/rtl/verilog/