URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [bench/] - Rev 69

Rev	Log message	Author	Age	Path
56	Added support for GDB hardware watchpoints, which can co-exist with hardware watchpoints set by AdvancedWatchpointControl. Added support for two new packets in adv_jtag_bridge for compatibility with GDB 7.x. Improved full-system testbench for adv_dbg_if, now includes the same OR1K self-test used by adv_jtag_bridge.	nyawn	4861d 12h	/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/
42	Added (experimental) Actel UJTAG TAP core. Added JTAG serial port feature to debug hardware core and JTAG bridge program. Added more speedups for USB JTAG cables to bridge program - USB-Blaster users should now see ~30k/sec upload speeds. Updated documentation.	nyawn	5180d 21h	/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/
32	Added a hi-speed mode via a change in protocol in the adv_dbg_if core. This should provide an order-of-magnitude speed improvement for some USB JTAG cables. Updated adv_jtag_bridge to match. Updated adv_dbg_if testbenches. Updated documents to reflect the new hi-speed mode. Added alternate USB-Blaster driver based on libftdi, donated by Xianfeng Zeng. Various bugfixes.	nyawn	5253d 14h	/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/
8	Moved sub-modules to the correct subdirectories.	nyawn	5497d 14h	/adv_debug_sys/trunk/Hardware/adv_dbg_if/bench/
3	HDL cores which make up the hardware portion of the Advanced Debug System.	nyawn	5497d 14h	/adv_debug_sys/trunk/adv_dbg_if/bench/