URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [trunk/] [Hardware/] [altera_virtual_jtag/] - Rev 69

Rev	Log message	Author	Age	Path
34	Restored changes accidentally backed out by previous commit. Removed CVS logs.	nyawn	5247d 07h	/adv_debug_sys/trunk/Hardware/altera_virtual_jtag/
32	Added a hi-speed mode via a change in protocol in the adv_dbg_if core. This should provide an order-of-magnitude speed improvement for some USB JTAG cables. Updated adv_jtag_bridge to match. Updated adv_dbg_if testbenches. Updated documents to reflect the new hi-speed mode. Added alternate USB-Blaster driver based on libftdi, donated by Xianfeng Zeng. Various bugfixes.	nyawn	5248d 04h	/adv_debug_sys/trunk/Hardware/altera_virtual_jtag/
30	Fix copy/paste error in copyright header: replaced verilog-style comments with VHDL comments.	nyawn	5360d 08h	/adv_debug_sys/trunk/Hardware/altera_virtual_jtag/
14	Added support for the legacy hardware debug unit (debug_if) to adv_jtag_bridge. Re-factored adv_jtag_bridge, removed many compilation warnings. Renamed some signals in the TAP cores for clarity. Updated documents.	nyawn	5463d 05h	/adv_debug_sys/trunk/Hardware/altera_virtual_jtag/
8	Moved sub-modules to the correct subdirectories.	nyawn	5492d 04h	/adv_debug_sys/trunk/Hardware/altera_virtual_jtag/
3	HDL cores which make up the hardware portion of the Advanced Debug System.	nyawn	5492d 05h	/adv_debug_sys/trunk/altera_virtual_jtag/