URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [branches/] [AEMB2_712/] - Rev 191

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5572d 14h	/aemb/branches/AEMB2_712/
77	This commit was manufactured by cvs2svn to create branch 'AEMB2_712'.		6030d 14h	/branches/AEMB2_712/
76	initial	sybreon	6030d 14h	/trunk/
74	Minor code cleanup.	sybreon	6037d 16h	/trunk/
73	Moved simulation kernel into code.	sybreon	6037d 16h	/trunk/
72	Minor code cleanup.	sybreon	6037d 16h	/trunk/
71	Old version deprecated.	sybreon	6044d 19h	/trunk/
70	Change interrupt to positive level triggered interrupts.	sybreon	6045d 18h	/trunk/
69	Removed unnecessary byte acrobatics with VMEM data.	sybreon	6047d 14h	/trunk/
68	Generate VMEM instead of HEX dumps of programme.	sybreon	6047d 14h	/trunk/
67	Minor simulation fixes.	sybreon	6049d 13h	/trunk/
66	Added fsl_tag_o to FSL bus (tag either address or data).	sybreon	6051d 11h	/trunk/
65	Fixed minor typo causing synthesis failure.	sybreon	6053d 00h	/trunk/
64	Fixed minor interrupt test typo.	sybreon	6053d 09h	/trunk/
63	Fixed interrupt signal synchronisation.	sybreon	6053d 09h	/trunk/
62	Fixed minor typo.	sybreon	6053d 10h	/trunk/
61	Changed interrupt handling system (reported by M. Ettus).	sybreon	6053d 11h	/trunk/
60	Added interrupt test routine.	sybreon	6053d 11h	/trunk/
59	Added posedge/negedge bus interface. Modified interrupt test system.	sybreon	6053d 11h	/trunk/
58	Updated simulation to also check BRI 0x00 instruction.	sybreon	6054d 09h	/trunk/