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[/] [aemb/] [branches/] [AEMB2_712/] - Rev 36

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Rev Log message Author Age Path
36 Removed asynchronous reset signal. sybreon 6325d 16h /aemb/branches/AEMB2_712/
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6326d 13h /aemb/branches/AEMB2_712/
34 Corrected speed issues after rev 1.9 update. sybreon 6327d 03h /aemb/branches/AEMB2_712/
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6342d 10h /aemb/branches/AEMB2_712/
32 Modified compilation sequence. sybreon 6342d 10h /aemb/branches/AEMB2_712/
31 Removed byte acrobatics. sybreon 6342d 10h /aemb/branches/AEMB2_712/
30 Minor updates as sw/c/aeMB_testbench.c got updated. sybreon 6345d 10h /aemb/branches/AEMB2_712/
29 Added code documentation.
Added new tests that test floating point, modulo arithmetic and multiplication/division.		 sybreon 6345d 10h /aemb/branches/AEMB2_712/
28 Fixed simulation bug. sybreon 6345d 10h /aemb/branches/AEMB2_712/
27 Removed some unnecessary bubble control. sybreon 6345d 21h /aemb/branches/AEMB2_712/
26 Fixed minor synthesis bug. sybreon 6345d 21h /aemb/branches/AEMB2_712/
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6346d 01h /aemb/branches/AEMB2_712/
24 Made minor performance optimisations. sybreon 6346d 11h /aemb/branches/AEMB2_712/
23 Fixed minor simulation bug. sybreon 6347d 03h /aemb/branches/AEMB2_712/
22 Added support for 8-bit and 16-bit data types. sybreon 6347d 03h /aemb/branches/AEMB2_712/
21 Added hierarchy block diagram. sybreon 6357d 09h /aemb/branches/AEMB2_712/
20 Added basic documentation doc/aeMB_datasheet.pdf sybreon 6357d 23h /aemb/branches/AEMB2_712/
19 Added initial unified memory core. sybreon 6359d 12h /aemb/branches/AEMB2_712/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6360d 05h /aemb/branches/AEMB2_712/
17 Cosmetic changes sybreon 6361d 09h /aemb/branches/AEMB2_712/

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