OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [branches/] [AEMB2_712/] [rtl/] [verilog/] - Rev 195

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
191 New directory structure. root 5590d 04h /aemb/branches/AEMB2_712/rtl/verilog/
77 This commit was manufactured by cvs2svn to create branch 'AEMB2_712'. 6048d 04h /aemb/branches/AEMB2_712/rtl/verilog/
76 initial sybreon 6048d 04h /aemb/branches/AEMB2_712/rtl/verilog/
73 Moved simulation kernel into code. sybreon 6055d 06h /aemb/branches/AEMB2_712/rtl/verilog/
72 Minor code cleanup. sybreon 6055d 06h /aemb/branches/AEMB2_712/rtl/verilog/
71 Old version deprecated. sybreon 6062d 09h /aemb/branches/AEMB2_712/rtl/verilog/
70 Change interrupt to positive level triggered interrupts. sybreon 6063d 08h /aemb/branches/AEMB2_712/rtl/verilog/
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6069d 01h /aemb/branches/AEMB2_712/rtl/verilog/
65 Fixed minor typo causing synthesis failure. sybreon 6070d 13h /aemb/branches/AEMB2_712/rtl/verilog/
63 Fixed interrupt signal synchronisation. sybreon 6070d 23h /aemb/branches/AEMB2_712/rtl/verilog/
62 Fixed minor typo. sybreon 6071d 00h /aemb/branches/AEMB2_712/rtl/verilog/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6071d 01h /aemb/branches/AEMB2_712/rtl/verilog/
56 Parameterised optional components into aeMB_xecu.v sybreon 6074d 23h /aemb/branches/AEMB2_712/rtl/verilog/
55 Upgraded license to LGPLv3.
Significant performance optimisations.
sybreon 6075d 06h /aemb/branches/AEMB2_712/rtl/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6076d 02h /aemb/branches/AEMB2_712/rtl/verilog/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6077d 05h /aemb/branches/AEMB2_712/rtl/verilog/
50 Parameterised optional components. sybreon 6077d 09h /aemb/branches/AEMB2_712/rtl/verilog/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6081d 17h /aemb/branches/AEMB2_712/rtl/verilog/
45 Minor code cleanup. sybreon 6082d 14h /aemb/branches/AEMB2_712/rtl/verilog/
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.
sybreon 6083d 04h /aemb/branches/AEMB2_712/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.