URL https://opencores.org/ocsvn/aemb/aemb/trunk

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[/] [aemb/] [branches/] [AEMB2_712/] [sim/] - Rev 30

Rev	Log message	Author	Age	Path
30	Minor updates as sw/c/aeMB_testbench.c got updated.	sybreon	6345d 03h	/aemb/branches/AEMB2_712/sim/
22	Added support for 8-bit and 16-bit data types.	sybreon	6346d 20h	/aemb/branches/AEMB2_712/sim/
19	Added initial unified memory core.	sybreon	6359d 05h	/aemb/branches/AEMB2_712/sim/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6359d 22h	/aemb/branches/AEMB2_712/sim/
15	Removed ROM file. Please generate it from the SW directory.	sybreon	6368d 04h	/aemb/branches/AEMB2_712/sim/
13	Fibonacci rom	sybreon	6368d 12h	/aemb/branches/AEMB2_712/sim/
2	initial import	sybreon	6394d 00h	/aemb/branches/AEMB2_712/sim/