URL https://opencores.org/ocsvn/aemb/aemb/trunk

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[/] [aemb/] [branches/] [AEMB2_712/] [sim/] - Rev 50

Rev	Log message	Author	Age	Path
50	Parameterised optional components.	sybreon	6125d 06h	/aemb/branches/AEMB2_712/sim/
49	Added random seed for simulation.	sybreon	6128d 10h	/aemb/branches/AEMB2_712/sim/
43	Added interrupt simulation. Changed "human readable" simulation output.	sybreon	6131d 01h	/aemb/branches/AEMB2_712/sim/
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6131d 17h	/aemb/branches/AEMB2_712/sim/
39	Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.	sybreon	6142d 01h	/aemb/branches/AEMB2_712/sim/
38	Added interrupt support.	sybreon	6287d 02h	/aemb/branches/AEMB2_712/sim/
31	Removed byte acrobatics.	sybreon	6317d 05h	/aemb/branches/AEMB2_712/sim/
30	Minor updates as sw/c/aeMB_testbench.c got updated.	sybreon	6320d 05h	/aemb/branches/AEMB2_712/sim/
22	Added support for 8-bit and 16-bit data types.	sybreon	6321d 22h	/aemb/branches/AEMB2_712/sim/
19	Added initial unified memory core.	sybreon	6334d 08h	/aemb/branches/AEMB2_712/sim/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6335d 00h	/aemb/branches/AEMB2_712/sim/
15	Removed ROM file. Please generate it from the SW directory.	sybreon	6343d 07h	/aemb/branches/AEMB2_712/sim/
13	Fibonacci rom	sybreon	6343d 14h	/aemb/branches/AEMB2_712/sim/
2	initial import	sybreon	6369d 03h	/aemb/branches/AEMB2_712/sim/