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[/] [aemb/] [branches/] [AEMB2_712/] [sim/] - Rev 52

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Rev Log message Author Age Path
52 Added log output to iverilog.log sybreon 6216d 10h /aemb/branches/AEMB2_712/sim/
50 Parameterised optional components. sybreon 6217d 17h /aemb/branches/AEMB2_712/sim/
49 Added random seed for simulation. sybreon 6220d 20h /aemb/branches/AEMB2_712/sim/
43 Added interrupt simulation.
Changed "human readable" simulation output.		 sybreon 6223d 12h /aemb/branches/AEMB2_712/sim/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6224d 03h /aemb/branches/AEMB2_712/sim/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6234d 12h /aemb/branches/AEMB2_712/sim/
38 Added interrupt support. sybreon 6379d 12h /aemb/branches/AEMB2_712/sim/
31 Removed byte acrobatics. sybreon 6409d 15h /aemb/branches/AEMB2_712/sim/
30 Minor updates as sw/c/aeMB_testbench.c got updated. sybreon 6412d 16h /aemb/branches/AEMB2_712/sim/
22 Added support for 8-bit and 16-bit data types. sybreon 6414d 09h /aemb/branches/AEMB2_712/sim/
19 Added initial unified memory core. sybreon 6426d 18h /aemb/branches/AEMB2_712/sim/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6427d 11h /aemb/branches/AEMB2_712/sim/
15 Removed ROM file. Please generate it from the SW directory. sybreon 6435d 17h /aemb/branches/AEMB2_712/sim/
13 Fibonacci rom sybreon 6436d 00h /aemb/branches/AEMB2_712/sim/
2 initial import sybreon 6461d 13h /aemb/branches/AEMB2_712/sim/

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