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[/] [aemb/] [branches/] [AEMB2_712/] [sim/] [verilog/] - Rev 195

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Rev Log message Author Age Path
191 New directory structure. root 5614d 21h /aemb/branches/AEMB2_712/sim/verilog/
77 This commit was manufactured by cvs2svn to create branch 'AEMB2_712'. 6072d 21h /aemb/branches/AEMB2_712/sim/verilog/
73 Moved simulation kernel into code. sybreon 6079d 23h /aemb/branches/AEMB2_712/sim/verilog/
71 Old version deprecated. sybreon 6087d 02h /aemb/branches/AEMB2_712/sim/verilog/
69 Removed unnecessary byte acrobatics with VMEM data. sybreon 6089d 21h /aemb/branches/AEMB2_712/sim/verilog/
67 Minor simulation fixes. sybreon 6091d 20h /aemb/branches/AEMB2_712/sim/verilog/
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6095d 17h /aemb/branches/AEMB2_712/sim/verilog/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6096d 16h /aemb/branches/AEMB2_712/sim/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6100d 19h /aemb/branches/AEMB2_712/sim/verilog/
50 Parameterised optional components. sybreon 6102d 01h /aemb/branches/AEMB2_712/sim/verilog/
49 Added random seed for simulation. sybreon 6105d 05h /aemb/branches/AEMB2_712/sim/verilog/
43 Added interrupt simulation.
Changed "human readable" simulation output.		 sybreon 6107d 20h /aemb/branches/AEMB2_712/sim/verilog/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6108d 12h /aemb/branches/AEMB2_712/sim/verilog/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6118d 20h /aemb/branches/AEMB2_712/sim/verilog/
38 Added interrupt support. sybreon 6263d 21h /aemb/branches/AEMB2_712/sim/verilog/
31 Removed byte acrobatics. sybreon 6294d 00h /aemb/branches/AEMB2_712/sim/verilog/
30 Minor updates as sw/c/aeMB_testbench.c got updated. sybreon 6297d 00h /aemb/branches/AEMB2_712/sim/verilog/
22 Added support for 8-bit and 16-bit data types. sybreon 6298d 17h /aemb/branches/AEMB2_712/sim/verilog/
19 Added initial unified memory core. sybreon 6311d 03h /aemb/branches/AEMB2_712/sim/verilog/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6311d 19h /aemb/branches/AEMB2_712/sim/verilog/

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