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[/] [aemb/] [branches/] [DEV_SYBREON/] - Rev 27

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Rev Log message Author Age Path
27 Removed some unnecessary bubble control. sybreon 6343d 05h /aemb/branches/DEV_SYBREON/
26 Fixed minor synthesis bug. sybreon 6343d 05h /aemb/branches/DEV_SYBREON/
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6343d 09h /aemb/branches/DEV_SYBREON/
24 Made minor performance optimisations. sybreon 6343d 19h /aemb/branches/DEV_SYBREON/
23 Fixed minor simulation bug. sybreon 6344d 10h /aemb/branches/DEV_SYBREON/
22 Added support for 8-bit and 16-bit data types. sybreon 6344d 11h /aemb/branches/DEV_SYBREON/
21 Added hierarchy block diagram. sybreon 6354d 16h /aemb/branches/DEV_SYBREON/
20 Added basic documentation doc/aeMB_datasheet.pdf sybreon 6355d 06h /aemb/branches/DEV_SYBREON/
19 Added initial unified memory core. sybreon 6356d 20h /aemb/branches/DEV_SYBREON/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6357d 13h /aemb/branches/DEV_SYBREON/
17 Cosmetic changes sybreon 6358d 17h /aemb/branches/DEV_SYBREON/
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.		 sybreon 6359d 05h /aemb/branches/DEV_SYBREON/
15 Removed ROM file. Please generate it from the SW directory. sybreon 6365d 19h /aemb/branches/DEV_SYBREON/
14 Added initial interrupt/exception support. sybreon 6365d 19h /aemb/branches/DEV_SYBREON/
13 Fibonacci rom sybreon 6366d 03h /aemb/branches/DEV_SYBREON/
12 Minor changes sybreon 6366d 03h /aemb/branches/DEV_SYBREON/
11 Removed unused signals sybreon 6366d 03h /aemb/branches/DEV_SYBREON/
10 Fixed minor bugs sybreon 6366d 03h /aemb/branches/DEV_SYBREON/
9 Extended testbench code sybreon 6366d 03h /aemb/branches/DEV_SYBREON/
8 Fixed memory read-write data hazard sybreon 6366d 03h /aemb/branches/DEV_SYBREON/

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