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Rev Log message Author Age Path
32 Modified compilation sequence. sybreon 6302d 07h /aemb/branches/DEV_SYBREON/
31 Removed byte acrobatics. sybreon 6302d 07h /aemb/branches/DEV_SYBREON/
30 Minor updates as sw/c/aeMB_testbench.c got updated. sybreon 6305d 08h /aemb/branches/DEV_SYBREON/
29 Added code documentation.
Added new tests that test floating point, modulo arithmetic and multiplication/division.		 sybreon 6305d 08h /aemb/branches/DEV_SYBREON/
28 Fixed simulation bug. sybreon 6305d 08h /aemb/branches/DEV_SYBREON/
27 Removed some unnecessary bubble control. sybreon 6305d 19h /aemb/branches/DEV_SYBREON/
26 Fixed minor synthesis bug. sybreon 6305d 19h /aemb/branches/DEV_SYBREON/
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6305d 23h /aemb/branches/DEV_SYBREON/
24 Made minor performance optimisations. sybreon 6306d 09h /aemb/branches/DEV_SYBREON/
23 Fixed minor simulation bug. sybreon 6307d 01h /aemb/branches/DEV_SYBREON/
22 Added support for 8-bit and 16-bit data types. sybreon 6307d 01h /aemb/branches/DEV_SYBREON/
21 Added hierarchy block diagram. sybreon 6317d 07h /aemb/branches/DEV_SYBREON/
20 Added basic documentation doc/aeMB_datasheet.pdf sybreon 6317d 21h /aemb/branches/DEV_SYBREON/
19 Added initial unified memory core. sybreon 6319d 10h /aemb/branches/DEV_SYBREON/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6320d 03h /aemb/branches/DEV_SYBREON/
17 Cosmetic changes sybreon 6321d 07h /aemb/branches/DEV_SYBREON/
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.		 sybreon 6321d 19h /aemb/branches/DEV_SYBREON/
15 Removed ROM file. Please generate it from the SW directory. sybreon 6328d 09h /aemb/branches/DEV_SYBREON/
14 Added initial interrupt/exception support. sybreon 6328d 09h /aemb/branches/DEV_SYBREON/
13 Fibonacci rom sybreon 6328d 17h /aemb/branches/DEV_SYBREON/

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