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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] - Rev 100

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Rev Log message Author Age Path
100 multiplier issues sybreon 6033d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
99 Minor cleanup sybreon 6044d 20h /aemb/branches/DEV_SYBREON/rtl/verilog/
96 Stalls pipeline on MUL/BSF instructions results in minor speed improvements. sybreon 6047d 22h /aemb/branches/DEV_SYBREON/rtl/verilog/
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6050d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
94 Prevent fHZD & rBRA[1] sybreon 6051d 22h /aemb/branches/DEV_SYBREON/rtl/verilog/
93 Minor enable fix sybreon 6051d 22h /aemb/branches/DEV_SYBREON/rtl/verilog/
92 Partitioned simulation model. sybreon 6055d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
91 Made idle thread PC track main PC. sybreon 6056d 07h /aemb/branches/DEV_SYBREON/rtl/verilog/
90 Fixed Carry bit bug. sybreon 6056d 07h /aemb/branches/DEV_SYBREON/rtl/verilog/
89 Changed simulation kernel. sybreon 6056d 07h /aemb/branches/DEV_SYBREON/rtl/verilog/
88 Minor optimisations. sybreon 6057d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
86 Some optimisations. sybreon 6057d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
85 Replaced OF/ID blocks with combined block. sybreon 6057d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
84 Added interrupt support. sybreon 6057d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
83 Combined ID/OF blocks. sybreon 6057d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
82 Further optimisations (speed + size). sybreon 6059d 23h /aemb/branches/DEV_SYBREON/rtl/verilog/
81 Code cleanup + minor speed regression. sybreon 6060d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
80 Minor optimisations (~10% faster) sybreon 6061d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
78 initial import sybreon 6062d 20h /aemb/branches/DEV_SYBREON/rtl/verilog/
76 initial sybreon 6066d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/

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