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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] - Rev 207

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Rev Log message Author Age Path
191 New directory structure. root 5589d 15h /aemb/branches/DEV_SYBREON/rtl/verilog/
115 This commit was manufactured by cvs2svn to create branch 'DEV_SYBREON'. 5921d 18h /aemb/branches/DEV_SYBREON/rtl/verilog/
114 changed MSR bits sybreon 5921d 18h /aemb/branches/DEV_SYBREON/rtl/verilog/
105 Patch interrupt bug. sybreon 6003d 09h /aemb/branches/DEV_SYBREON/rtl/verilog/
103 Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) sybreon 6004d 18h /aemb/branches/DEV_SYBREON/rtl/verilog/
102 Fix MTS during interrupt vectoring bug (reported by M. Ettus). sybreon 6004d 18h /aemb/branches/DEV_SYBREON/rtl/verilog/
101 Made multiplier pause with pipeline sybreon 6014d 15h /aemb/branches/DEV_SYBREON/rtl/verilog/
100 multiplier issues sybreon 6014d 15h /aemb/branches/DEV_SYBREON/rtl/verilog/
99 Minor cleanup sybreon 6026d 10h /aemb/branches/DEV_SYBREON/rtl/verilog/
96 Stalls pipeline on MUL/BSF instructions results in minor speed improvements. sybreon 6029d 12h /aemb/branches/DEV_SYBREON/rtl/verilog/
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6031d 13h /aemb/branches/DEV_SYBREON/rtl/verilog/
94 Prevent fHZD & rBRA[1] sybreon 6033d 11h /aemb/branches/DEV_SYBREON/rtl/verilog/
93 Minor enable fix sybreon 6033d 12h /aemb/branches/DEV_SYBREON/rtl/verilog/
92 Partitioned simulation model. sybreon 6036d 15h /aemb/branches/DEV_SYBREON/rtl/verilog/
91 Made idle thread PC track main PC. sybreon 6037d 21h /aemb/branches/DEV_SYBREON/rtl/verilog/
90 Fixed Carry bit bug. sybreon 6037d 21h /aemb/branches/DEV_SYBREON/rtl/verilog/
89 Changed simulation kernel. sybreon 6037d 21h /aemb/branches/DEV_SYBREON/rtl/verilog/
88 Minor optimisations. sybreon 6038d 13h /aemb/branches/DEV_SYBREON/rtl/verilog/
86 Some optimisations. sybreon 6039d 07h /aemb/branches/DEV_SYBREON/rtl/verilog/
85 Replaced OF/ID blocks with combined block. sybreon 6039d 07h /aemb/branches/DEV_SYBREON/rtl/verilog/

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