OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] - Rev 27

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
27 Removed some unnecessary bubble control. sybreon 6283d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
26 Fixed minor synthesis bug. sybreon 6283d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6283d 23h /aemb/branches/DEV_SYBREON/rtl/verilog/
24 Made minor performance optimisations. sybreon 6284d 09h /aemb/branches/DEV_SYBREON/rtl/verilog/
23 Fixed minor simulation bug. sybreon 6285d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
22 Added support for 8-bit and 16-bit data types. sybreon 6285d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
19 Added initial unified memory core. sybreon 6297d 11h /aemb/branches/DEV_SYBREON/rtl/verilog/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6298d 03h /aemb/branches/DEV_SYBREON/rtl/verilog/
17 Cosmetic changes sybreon 6299d 07h /aemb/branches/DEV_SYBREON/rtl/verilog/
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.		 sybreon 6299d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
14 Added initial interrupt/exception support. sybreon 6306d 09h /aemb/branches/DEV_SYBREON/rtl/verilog/
11 Removed unused signals sybreon 6306d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
10 Fixed minor bugs sybreon 6306d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
9 Extended testbench code sybreon 6306d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
8 Fixed memory read-write data hazard sybreon 6306d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
7 Added CMP instruction sybreon 6306d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
5 Fixed endian correction issues on data bus. sybreon 6307d 09h /aemb/branches/DEV_SYBREON/rtl/verilog/
4 Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee. sybreon 6315d 11h /aemb/branches/DEV_SYBREON/rtl/verilog/
3 initial import sybreon 6332d 06h /aemb/branches/DEV_SYBREON/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.