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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] - Rev 34

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Rev Log message Author Age Path
34 Corrected speed issues after rev 1.9 update. sybreon 6265d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6280d 08h /aemb/branches/DEV_SYBREON/rtl/verilog/
31 Removed byte acrobatics. sybreon 6280d 08h /aemb/branches/DEV_SYBREON/rtl/verilog/
28 Fixed simulation bug. sybreon 6283d 08h /aemb/branches/DEV_SYBREON/rtl/verilog/
27 Removed some unnecessary bubble control. sybreon 6283d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
26 Fixed minor synthesis bug. sybreon 6283d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6283d 23h /aemb/branches/DEV_SYBREON/rtl/verilog/
24 Made minor performance optimisations. sybreon 6284d 09h /aemb/branches/DEV_SYBREON/rtl/verilog/
23 Fixed minor simulation bug. sybreon 6285d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
22 Added support for 8-bit and 16-bit data types. sybreon 6285d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
19 Added initial unified memory core. sybreon 6297d 10h /aemb/branches/DEV_SYBREON/rtl/verilog/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6298d 03h /aemb/branches/DEV_SYBREON/rtl/verilog/
17 Cosmetic changes sybreon 6299d 07h /aemb/branches/DEV_SYBREON/rtl/verilog/
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.		 sybreon 6299d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
14 Added initial interrupt/exception support. sybreon 6306d 09h /aemb/branches/DEV_SYBREON/rtl/verilog/
11 Removed unused signals sybreon 6306d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
10 Fixed minor bugs sybreon 6306d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
9 Extended testbench code sybreon 6306d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
8 Fixed memory read-write data hazard sybreon 6306d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
7 Added CMP instruction sybreon 6306d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/

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