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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] - Rev 55

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Rev Log message Author Age Path
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6086d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6086d 21h /aemb/branches/DEV_SYBREON/rtl/verilog/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6088d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
50 Parameterised optional components. sybreon 6088d 04h /aemb/branches/DEV_SYBREON/rtl/verilog/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6092d 13h /aemb/branches/DEV_SYBREON/rtl/verilog/
45 Minor code cleanup. sybreon 6093d 09h /aemb/branches/DEV_SYBREON/rtl/verilog/
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6093d 23h /aemb/branches/DEV_SYBREON/rtl/verilog/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6094d 15h /aemb/branches/DEV_SYBREON/rtl/verilog/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6104d 23h /aemb/branches/DEV_SYBREON/rtl/verilog/
38 Added interrupt support. sybreon 6249d 23h /aemb/branches/DEV_SYBREON/rtl/verilog/
36 Removed asynchronous reset signal. sybreon 6263d 09h /aemb/branches/DEV_SYBREON/rtl/verilog/
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6264d 05h /aemb/branches/DEV_SYBREON/rtl/verilog/
34 Corrected speed issues after rev 1.9 update. sybreon 6264d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6280d 02h /aemb/branches/DEV_SYBREON/rtl/verilog/
31 Removed byte acrobatics. sybreon 6280d 02h /aemb/branches/DEV_SYBREON/rtl/verilog/
28 Fixed simulation bug. sybreon 6283d 03h /aemb/branches/DEV_SYBREON/rtl/verilog/
27 Removed some unnecessary bubble control. sybreon 6283d 14h /aemb/branches/DEV_SYBREON/rtl/verilog/
26 Fixed minor synthesis bug. sybreon 6283d 14h /aemb/branches/DEV_SYBREON/rtl/verilog/
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6283d 18h /aemb/branches/DEV_SYBREON/rtl/verilog/
24 Made minor performance optimisations. sybreon 6284d 04h /aemb/branches/DEV_SYBREON/rtl/verilog/

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