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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] - Rev 85

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Rev Log message Author Age Path
85 Replaced OF/ID blocks with combined block. sybreon 6057d 13h /aemb/branches/DEV_SYBREON/rtl/verilog/
84 Added interrupt support. sybreon 6057d 13h /aemb/branches/DEV_SYBREON/rtl/verilog/
83 Combined ID/OF blocks. sybreon 6057d 13h /aemb/branches/DEV_SYBREON/rtl/verilog/
82 Further optimisations (speed + size). sybreon 6059d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
81 Code cleanup + minor speed regression. sybreon 6059d 21h /aemb/branches/DEV_SYBREON/rtl/verilog/
80 Minor optimisations (~10% faster) sybreon 6060d 22h /aemb/branches/DEV_SYBREON/rtl/verilog/
78 initial import sybreon 6062d 16h /aemb/branches/DEV_SYBREON/rtl/verilog/
76 initial sybreon 6065d 22h /aemb/branches/DEV_SYBREON/rtl/verilog/
73 Moved simulation kernel into code. sybreon 6073d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
72 Minor code cleanup. sybreon 6073d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
71 Old version deprecated. sybreon 6080d 03h /aemb/branches/DEV_SYBREON/rtl/verilog/
70 Change interrupt to positive level triggered interrupts. sybreon 6081d 02h /aemb/branches/DEV_SYBREON/rtl/verilog/
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6086d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
65 Fixed minor typo causing synthesis failure. sybreon 6088d 07h /aemb/branches/DEV_SYBREON/rtl/verilog/
63 Fixed interrupt signal synchronisation. sybreon 6088d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
62 Fixed minor typo. sybreon 6088d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6088d 19h /aemb/branches/DEV_SYBREON/rtl/verilog/
56 Parameterised optional components into aeMB_xecu.v sybreon 6092d 17h /aemb/branches/DEV_SYBREON/rtl/verilog/
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6093d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6093d 20h /aemb/branches/DEV_SYBREON/rtl/verilog/

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