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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] - Rev 89

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Rev Log message Author Age Path
89 Changed simulation kernel. sybreon 6085d 16h /aemb/branches/DEV_SYBREON/rtl/verilog/
88 Minor optimisations. sybreon 6086d 09h /aemb/branches/DEV_SYBREON/rtl/verilog/
86 Some optimisations. sybreon 6087d 02h /aemb/branches/DEV_SYBREON/rtl/verilog/
85 Replaced OF/ID blocks with combined block. sybreon 6087d 02h /aemb/branches/DEV_SYBREON/rtl/verilog/
84 Added interrupt support. sybreon 6087d 02h /aemb/branches/DEV_SYBREON/rtl/verilog/
83 Combined ID/OF blocks. sybreon 6087d 02h /aemb/branches/DEV_SYBREON/rtl/verilog/
82 Further optimisations (speed + size). sybreon 6089d 08h /aemb/branches/DEV_SYBREON/rtl/verilog/
81 Code cleanup + minor speed regression. sybreon 6089d 09h /aemb/branches/DEV_SYBREON/rtl/verilog/
80 Minor optimisations (~10% faster) sybreon 6090d 10h /aemb/branches/DEV_SYBREON/rtl/verilog/
78 initial import sybreon 6092d 05h /aemb/branches/DEV_SYBREON/rtl/verilog/
76 initial sybreon 6095d 10h /aemb/branches/DEV_SYBREON/rtl/verilog/
73 Moved simulation kernel into code. sybreon 6102d 12h /aemb/branches/DEV_SYBREON/rtl/verilog/
72 Minor code cleanup. sybreon 6102d 12h /aemb/branches/DEV_SYBREON/rtl/verilog/
71 Old version deprecated. sybreon 6109d 15h /aemb/branches/DEV_SYBREON/rtl/verilog/
70 Change interrupt to positive level triggered interrupts. sybreon 6110d 14h /aemb/branches/DEV_SYBREON/rtl/verilog/
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6116d 07h /aemb/branches/DEV_SYBREON/rtl/verilog/
65 Fixed minor typo causing synthesis failure. sybreon 6117d 20h /aemb/branches/DEV_SYBREON/rtl/verilog/
63 Fixed interrupt signal synchronisation. sybreon 6118d 06h /aemb/branches/DEV_SYBREON/rtl/verilog/
62 Fixed minor typo. sybreon 6118d 06h /aemb/branches/DEV_SYBREON/rtl/verilog/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6118d 07h /aemb/branches/DEV_SYBREON/rtl/verilog/

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