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[/] [aemb/] [branches/] [DEV_SYBREON/] [rtl/] [verilog/] - Rev 94

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Rev Log message Author Age Path
94 Prevent fHZD & rBRA[1] sybreon 6082d 20h /aemb/branches/DEV_SYBREON/rtl/verilog/
93 Minor enable fix sybreon 6082d 20h /aemb/branches/DEV_SYBREON/rtl/verilog/
92 Partitioned simulation model. sybreon 6086d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
91 Made idle thread PC track main PC. sybreon 6087d 06h /aemb/branches/DEV_SYBREON/rtl/verilog/
90 Fixed Carry bit bug. sybreon 6087d 06h /aemb/branches/DEV_SYBREON/rtl/verilog/
89 Changed simulation kernel. sybreon 6087d 06h /aemb/branches/DEV_SYBREON/rtl/verilog/
88 Minor optimisations. sybreon 6087d 22h /aemb/branches/DEV_SYBREON/rtl/verilog/
86 Some optimisations. sybreon 6088d 15h /aemb/branches/DEV_SYBREON/rtl/verilog/
85 Replaced OF/ID blocks with combined block. sybreon 6088d 15h /aemb/branches/DEV_SYBREON/rtl/verilog/
84 Added interrupt support. sybreon 6088d 15h /aemb/branches/DEV_SYBREON/rtl/verilog/
83 Combined ID/OF blocks. sybreon 6088d 15h /aemb/branches/DEV_SYBREON/rtl/verilog/
82 Further optimisations (speed + size). sybreon 6090d 21h /aemb/branches/DEV_SYBREON/rtl/verilog/
81 Code cleanup + minor speed regression. sybreon 6090d 22h /aemb/branches/DEV_SYBREON/rtl/verilog/
80 Minor optimisations (~10% faster) sybreon 6091d 23h /aemb/branches/DEV_SYBREON/rtl/verilog/
78 initial import sybreon 6093d 18h /aemb/branches/DEV_SYBREON/rtl/verilog/
76 initial sybreon 6097d 00h /aemb/branches/DEV_SYBREON/rtl/verilog/
73 Moved simulation kernel into code. sybreon 6104d 01h /aemb/branches/DEV_SYBREON/rtl/verilog/
72 Minor code cleanup. sybreon 6104d 02h /aemb/branches/DEV_SYBREON/rtl/verilog/
71 Old version deprecated. sybreon 6111d 04h /aemb/branches/DEV_SYBREON/rtl/verilog/
70 Change interrupt to positive level triggered interrupts. sybreon 6112d 03h /aemb/branches/DEV_SYBREON/rtl/verilog/

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