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[/] [aemb/] [tags/] [AEMB_711/] - Rev 59

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Rev Log message Author Age Path
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6105d 20h /aemb/tags/AEMB_711/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6106d 19h /aemb/tags/AEMB_711/
57 Updated documentation to EDK32 version. sybreon 6108d 20h /aemb/tags/AEMB_711/
56 Parameterised optional components into aeMB_xecu.v sybreon 6109d 18h /aemb/tags/AEMB_711/
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6110d 02h /aemb/tags/AEMB_711/
54 Added some compilation optimisations. sybreon 6110d 22h /aemb/tags/AEMB_711/
53 Added GET/PUT support through a FSL bus. sybreon 6110d 22h /aemb/tags/AEMB_711/
52 Added log output to iverilog.log sybreon 6110d 22h /aemb/tags/AEMB_711/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6112d 01h /aemb/tags/AEMB_711/
50 Parameterised optional components. sybreon 6112d 04h /aemb/tags/AEMB_711/
49 Added random seed for simulation. sybreon 6115d 07h /aemb/tags/AEMB_711/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6116d 13h /aemb/tags/AEMB_711/
47 Added -msoft-float and -mxl-soft-div compiler flags. sybreon 6116d 13h /aemb/tags/AEMB_711/
46 Minor code cleanup. sybreon 6117d 10h /aemb/tags/AEMB_711/
45 Minor code cleanup. sybreon 6117d 10h /aemb/tags/AEMB_711/
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6117d 23h /aemb/tags/AEMB_711/
43 Added interrupt simulation.
Changed "human readable" simulation output.		 sybreon 6117d 23h /aemb/tags/AEMB_711/
42 Enable MSR_IE with software. sybreon 6118d 00h /aemb/tags/AEMB_711/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6118d 15h /aemb/tags/AEMB_711/
40 Recommended to compile code with -O2/3/s sybreon 6128d 23h /aemb/tags/AEMB_711/

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