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[/] [aemb/] [tags/] [AEMB_711/] [rtl/] [verilog/] - Rev 196

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Rev Log message Author Age Path
191 New directory structure. root 5602d 15h /aemb/tags/AEMB_711/rtl/verilog/
75 This commit was manufactured by cvs2svn to create tag 'AEMB_711'. 6067d 17h /aemb/tags/AEMB_711/rtl/verilog/
73 Moved simulation kernel into code. sybreon 6067d 17h /aemb/tags/AEMB_711/rtl/verilog/
72 Minor code cleanup. sybreon 6067d 17h /aemb/tags/AEMB_711/rtl/verilog/
71 Old version deprecated. sybreon 6074d 20h /aemb/tags/AEMB_711/rtl/verilog/
70 Change interrupt to positive level triggered interrupts. sybreon 6075d 19h /aemb/tags/AEMB_711/rtl/verilog/
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6081d 12h /aemb/tags/AEMB_711/rtl/verilog/
65 Fixed minor typo causing synthesis failure. sybreon 6083d 01h /aemb/tags/AEMB_711/rtl/verilog/
63 Fixed interrupt signal synchronisation. sybreon 6083d 10h /aemb/tags/AEMB_711/rtl/verilog/
62 Fixed minor typo. sybreon 6083d 11h /aemb/tags/AEMB_711/rtl/verilog/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6083d 12h /aemb/tags/AEMB_711/rtl/verilog/
56 Parameterised optional components into aeMB_xecu.v sybreon 6087d 10h /aemb/tags/AEMB_711/rtl/verilog/
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6087d 17h /aemb/tags/AEMB_711/rtl/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6088d 13h /aemb/tags/AEMB_711/rtl/verilog/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6089d 16h /aemb/tags/AEMB_711/rtl/verilog/
50 Parameterised optional components. sybreon 6089d 20h /aemb/tags/AEMB_711/rtl/verilog/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6094d 05h /aemb/tags/AEMB_711/rtl/verilog/
45 Minor code cleanup. sybreon 6095d 02h /aemb/tags/AEMB_711/rtl/verilog/
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6095d 15h /aemb/tags/AEMB_711/rtl/verilog/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6096d 07h /aemb/tags/AEMB_711/rtl/verilog/

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