URL https://opencores.org/ocsvn/aemb/aemb/trunk

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[/] [aemb/] [tags/] [AEMB_711/] [sim/] - Rev 49

Rev	Log message	Author	Age	Path
49	Added random seed for simulation.	sybreon	6115d 03h	/aemb/tags/AEMB_711/sim/
43	Added interrupt simulation. Changed "human readable" simulation output.	sybreon	6117d 19h	/aemb/tags/AEMB_711/sim/
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6118d 11h	/aemb/tags/AEMB_711/sim/
39	Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.	sybreon	6128d 19h	/aemb/tags/AEMB_711/sim/
38	Added interrupt support.	sybreon	6273d 20h	/aemb/tags/AEMB_711/sim/
31	Removed byte acrobatics.	sybreon	6303d 23h	/aemb/tags/AEMB_711/sim/
30	Minor updates as sw/c/aeMB_testbench.c got updated.	sybreon	6306d 23h	/aemb/tags/AEMB_711/sim/
22	Added support for 8-bit and 16-bit data types.	sybreon	6308d 16h	/aemb/tags/AEMB_711/sim/
19	Added initial unified memory core.	sybreon	6321d 01h	/aemb/tags/AEMB_711/sim/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6321d 18h	/aemb/tags/AEMB_711/sim/
15	Removed ROM file. Please generate it from the SW directory.	sybreon	6330d 00h	/aemb/tags/AEMB_711/sim/
13	Fibonacci rom	sybreon	6330d 08h	/aemb/tags/AEMB_711/sim/
2	initial import	sybreon	6355d 21h	/aemb/tags/AEMB_711/sim/