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[/] [aemb/] [tags/] [AEMB_711/] [sim/] [verilog/] - Rev 191

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Rev Log message Author Age Path
191 New directory structure. root 5600d 13h /aemb/tags/AEMB_711/sim/verilog/
75 This commit was manufactured by cvs2svn to create tag 'AEMB_711'. 6065d 15h /aemb/tags/AEMB_711/sim/verilog/
73 Moved simulation kernel into code. sybreon 6065d 15h /aemb/tags/AEMB_711/sim/verilog/
71 Old version deprecated. sybreon 6072d 18h /aemb/tags/AEMB_711/sim/verilog/
69 Removed unnecessary byte acrobatics with VMEM data. sybreon 6075d 13h /aemb/tags/AEMB_711/sim/verilog/
67 Minor simulation fixes. sybreon 6077d 12h /aemb/tags/AEMB_711/sim/verilog/
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6081d 10h /aemb/tags/AEMB_711/sim/verilog/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6082d 08h /aemb/tags/AEMB_711/sim/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6086d 11h /aemb/tags/AEMB_711/sim/verilog/
50 Parameterised optional components. sybreon 6087d 18h /aemb/tags/AEMB_711/sim/verilog/
49 Added random seed for simulation. sybreon 6090d 21h /aemb/tags/AEMB_711/sim/verilog/
43 Added interrupt simulation.
Changed "human readable" simulation output.		 sybreon 6093d 13h /aemb/tags/AEMB_711/sim/verilog/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6094d 05h /aemb/tags/AEMB_711/sim/verilog/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6104d 13h /aemb/tags/AEMB_711/sim/verilog/
38 Added interrupt support. sybreon 6249d 13h /aemb/tags/AEMB_711/sim/verilog/
31 Removed byte acrobatics. sybreon 6279d 16h /aemb/tags/AEMB_711/sim/verilog/
30 Minor updates as sw/c/aeMB_testbench.c got updated. sybreon 6282d 17h /aemb/tags/AEMB_711/sim/verilog/
22 Added support for 8-bit and 16-bit data types. sybreon 6284d 10h /aemb/tags/AEMB_711/sim/verilog/
19 Added initial unified memory core. sybreon 6296d 19h /aemb/tags/AEMB_711/sim/verilog/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6297d 12h /aemb/tags/AEMB_711/sim/verilog/

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