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[/] [aemb/] [tags/] [AEMB_7_05/] [rtl/] - Rev 206

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Rev	Log message	Author	Age	Path
191	New directory structure.	root	5586d 18h	/aemb/tags/AEMB_7_05/rtl/
37	This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'.		6249d 04h	/aemb/tags/AEMB_7_05/rtl/
36	Removed asynchronous reset signal.	sybreon	6249d 04h	/aemb/tags/AEMB_7_05/rtl/
35	Added async BRA/DLY signals for future clock, reset, and interrupt features.	sybreon	6250d 00h	/aemb/tags/AEMB_7_05/rtl/
34	Corrected speed issues after rev 1.9 update.	sybreon	6250d 14h	/aemb/tags/AEMB_7_05/rtl/
33	Fixed minor data hazard bug spotted by Matt Ettus.	sybreon	6265d 21h	/aemb/tags/AEMB_7_05/rtl/
31	Removed byte acrobatics.	sybreon	6265d 21h	/aemb/tags/AEMB_7_05/rtl/
28	Fixed simulation bug.	sybreon	6268d 22h	/aemb/tags/AEMB_7_05/rtl/
27	Removed some unnecessary bubble control.	sybreon	6269d 09h	/aemb/tags/AEMB_7_05/rtl/
26	Fixed minor synthesis bug.	sybreon	6269d 09h	/aemb/tags/AEMB_7_05/rtl/
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6269d 13h	/aemb/tags/AEMB_7_05/rtl/
24	Made minor performance optimisations.	sybreon	6269d 22h	/aemb/tags/AEMB_7_05/rtl/
23	Fixed minor simulation bug.	sybreon	6270d 14h	/aemb/tags/AEMB_7_05/rtl/
22	Added support for 8-bit and 16-bit data types.	sybreon	6270d 15h	/aemb/tags/AEMB_7_05/rtl/
19	Added initial unified memory core.	sybreon	6283d 00h	/aemb/tags/AEMB_7_05/rtl/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6283d 17h	/aemb/tags/AEMB_7_05/rtl/
17	Cosmetic changes	sybreon	6284d 20h	/aemb/tags/AEMB_7_05/rtl/
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6285d 08h	/aemb/tags/AEMB_7_05/rtl/
14	Added initial interrupt/exception support.	sybreon	6291d 23h	/aemb/tags/AEMB_7_05/rtl/
11	Removed unused signals	sybreon	6292d 07h	/aemb/tags/AEMB_7_05/rtl/

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[/] [aemb/] [tags/] [AEMB_7_05/] [rtl/] - Rev 206

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