URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [tags/] [AEMB_7_05/] [rtl/] - Rev 25

Rev	Log message	Author	Age	Path
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6284d 04h	/aemb/tags/AEMB_7_05/rtl/
24	Made minor performance optimisations.	sybreon	6284d 13h	/aemb/tags/AEMB_7_05/rtl/
23	Fixed minor simulation bug.	sybreon	6285d 05h	/aemb/tags/AEMB_7_05/rtl/
22	Added support for 8-bit and 16-bit data types.	sybreon	6285d 06h	/aemb/tags/AEMB_7_05/rtl/
19	Added initial unified memory core.	sybreon	6297d 15h	/aemb/tags/AEMB_7_05/rtl/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6298d 08h	/aemb/tags/AEMB_7_05/rtl/
17	Cosmetic changes	sybreon	6299d 11h	/aemb/tags/AEMB_7_05/rtl/
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6299d 23h	/aemb/tags/AEMB_7_05/rtl/
14	Added initial interrupt/exception support.	sybreon	6306d 14h	/aemb/tags/AEMB_7_05/rtl/
11	Removed unused signals	sybreon	6306d 22h	/aemb/tags/AEMB_7_05/rtl/
10	Fixed minor bugs	sybreon	6306d 22h	/aemb/tags/AEMB_7_05/rtl/
9	Extended testbench code	sybreon	6306d 22h	/aemb/tags/AEMB_7_05/rtl/
8	Fixed memory read-write data hazard	sybreon	6306d 22h	/aemb/tags/AEMB_7_05/rtl/
7	Added CMP instruction	sybreon	6306d 22h	/aemb/tags/AEMB_7_05/rtl/
5	Fixed endian correction issues on data bus.	sybreon	6307d 13h	/aemb/tags/AEMB_7_05/rtl/
4	Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee.	sybreon	6315d 16h	/aemb/tags/AEMB_7_05/rtl/
3	initial import	sybreon	6332d 10h	/aemb/tags/AEMB_7_05/rtl/