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[/] [aemb/] [tags/] [AEMB_7_05/] [rtl/] [verilog/] - Rev 196

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Rev Log message Author Age Path
191 New directory structure. root 5591d 04h /aemb/tags/AEMB_7_05/rtl/verilog/
37 This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'. 6253d 13h /aemb/tags/AEMB_7_05/rtl/verilog/
36 Removed asynchronous reset signal. sybreon 6253d 13h /aemb/tags/AEMB_7_05/rtl/verilog/
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6254d 10h /aemb/tags/AEMB_7_05/rtl/verilog/
34 Corrected speed issues after rev 1.9 update. sybreon 6254d 23h /aemb/tags/AEMB_7_05/rtl/verilog/
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6270d 06h /aemb/tags/AEMB_7_05/rtl/verilog/
31 Removed byte acrobatics. sybreon 6270d 06h /aemb/tags/AEMB_7_05/rtl/verilog/
28 Fixed simulation bug. sybreon 6273d 07h /aemb/tags/AEMB_7_05/rtl/verilog/
27 Removed some unnecessary bubble control. sybreon 6273d 18h /aemb/tags/AEMB_7_05/rtl/verilog/
26 Fixed minor synthesis bug. sybreon 6273d 18h /aemb/tags/AEMB_7_05/rtl/verilog/
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6273d 22h /aemb/tags/AEMB_7_05/rtl/verilog/
24 Made minor performance optimisations. sybreon 6274d 08h /aemb/tags/AEMB_7_05/rtl/verilog/
23 Fixed minor simulation bug. sybreon 6274d 23h /aemb/tags/AEMB_7_05/rtl/verilog/
22 Added support for 8-bit and 16-bit data types. sybreon 6275d 00h /aemb/tags/AEMB_7_05/rtl/verilog/
19 Added initial unified memory core. sybreon 6287d 09h /aemb/tags/AEMB_7_05/rtl/verilog/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6288d 02h /aemb/tags/AEMB_7_05/rtl/verilog/
17 Cosmetic changes sybreon 6289d 06h /aemb/tags/AEMB_7_05/rtl/verilog/
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.		 sybreon 6289d 18h /aemb/tags/AEMB_7_05/rtl/verilog/
14 Added initial interrupt/exception support. sybreon 6296d 08h /aemb/tags/AEMB_7_05/rtl/verilog/
11 Removed unused signals sybreon 6296d 16h /aemb/tags/AEMB_7_05/rtl/verilog/

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