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[/] [aemb/] [tags/] [AEMB_7_05/] [sim/] [verilog/] - Rev 206

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5590d 12h	/aemb/tags/AEMB_7_05/sim/verilog/
37	This commit was manufactured by cvs2svn to create tag 'AEMB_7_05'.		6252d 22h	/aemb/tags/AEMB_7_05/sim/verilog/
31	Removed byte acrobatics.	sybreon	6269d 15h	/aemb/tags/AEMB_7_05/sim/verilog/
30	Minor updates as sw/c/aeMB_testbench.c got updated.	sybreon	6272d 16h	/aemb/tags/AEMB_7_05/sim/verilog/
22	Added support for 8-bit and 16-bit data types.	sybreon	6274d 09h	/aemb/tags/AEMB_7_05/sim/verilog/
19	Added initial unified memory core.	sybreon	6286d 18h	/aemb/tags/AEMB_7_05/sim/verilog/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6287d 11h	/aemb/tags/AEMB_7_05/sim/verilog/