URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] - Rev 21

Rev	Log message	Author	Age	Path
21	Added hierarchy block diagram.	sybreon	6300d 05h	/aemb/trunk/
20	Added basic documentation doc/aeMB_datasheet.pdf	sybreon	6300d 19h	/aemb/trunk/
19	Added initial unified memory core.	sybreon	6302d 08h	/aemb/trunk/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6303d 01h	/aemb/trunk/
17	Cosmetic changes	sybreon	6304d 05h	/aemb/trunk/
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6304d 17h	/aemb/trunk/
15	Removed ROM file. Please generate it from the SW directory.	sybreon	6311d 07h	/aemb/trunk/
14	Added initial interrupt/exception support.	sybreon	6311d 07h	/aemb/trunk/
13	Fibonacci rom	sybreon	6311d 15h	/aemb/trunk/
12	Minor changes	sybreon	6311d 15h	/aemb/trunk/
11	Removed unused signals	sybreon	6311d 15h	/aemb/trunk/
10	Fixed minor bugs	sybreon	6311d 15h	/aemb/trunk/
9	Extended testbench code	sybreon	6311d 15h	/aemb/trunk/
8	Fixed memory read-write data hazard	sybreon	6311d 15h	/aemb/trunk/
7	Added CMP instruction	sybreon	6311d 15h	/aemb/trunk/
6	Fixed C code bug which passes the test	sybreon	6311d 15h	/aemb/trunk/
5	Fixed endian correction issues on data bus.	sybreon	6312d 07h	/aemb/trunk/
4	Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee.	sybreon	6320d 09h	/aemb/trunk/
3	initial import	sybreon	6337d 03h	/aemb/trunk/
2	initial import	sybreon	6337d 04h	/aemb/trunk/