URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] - Rev 26

Rev	Log message	Author	Age	Path
26	Fixed minor synthesis bug.	sybreon	6288d 10h	/aemb/trunk/
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6288d 14h	/aemb/trunk/
24	Made minor performance optimisations.	sybreon	6289d 00h	/aemb/trunk/
23	Fixed minor simulation bug.	sybreon	6289d 16h	/aemb/trunk/
22	Added support for 8-bit and 16-bit data types.	sybreon	6289d 16h	/aemb/trunk/
21	Added hierarchy block diagram.	sybreon	6299d 22h	/aemb/trunk/
20	Added basic documentation doc/aeMB_datasheet.pdf	sybreon	6300d 12h	/aemb/trunk/
19	Added initial unified memory core.	sybreon	6302d 01h	/aemb/trunk/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6302d 18h	/aemb/trunk/
17	Cosmetic changes	sybreon	6303d 22h	/aemb/trunk/
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6304d 10h	/aemb/trunk/
15	Removed ROM file. Please generate it from the SW directory.	sybreon	6311d 00h	/aemb/trunk/
14	Added initial interrupt/exception support.	sybreon	6311d 00h	/aemb/trunk/
13	Fibonacci rom	sybreon	6311d 08h	/aemb/trunk/
12	Minor changes	sybreon	6311d 08h	/aemb/trunk/
11	Removed unused signals	sybreon	6311d 08h	/aemb/trunk/
10	Fixed minor bugs	sybreon	6311d 08h	/aemb/trunk/
9	Extended testbench code	sybreon	6311d 08h	/aemb/trunk/
8	Fixed memory read-write data hazard	sybreon	6311d 08h	/aemb/trunk/
7	Added CMP instruction	sybreon	6311d 08h	/aemb/trunk/