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[/] [aemb/] [trunk/] - Rev 67

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Rev Log message Author Age Path
67 Minor simulation fixes. sybreon 6106d 09h /aemb/trunk/
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6108d 06h /aemb/trunk/
65 Fixed minor typo causing synthesis failure. sybreon 6109d 19h /aemb/trunk/
64 Fixed minor interrupt test typo. sybreon 6110d 05h /aemb/trunk/
63 Fixed interrupt signal synchronisation. sybreon 6110d 05h /aemb/trunk/
62 Fixed minor typo. sybreon 6110d 05h /aemb/trunk/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6110d 06h /aemb/trunk/
60 Added interrupt test routine. sybreon 6110d 06h /aemb/trunk/
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6110d 06h /aemb/trunk/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6111d 05h /aemb/trunk/
57 Updated documentation to EDK32 version. sybreon 6113d 06h /aemb/trunk/
56 Parameterised optional components into aeMB_xecu.v sybreon 6114d 04h /aemb/trunk/
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6114d 12h /aemb/trunk/
54 Added some compilation optimisations. sybreon 6115d 07h /aemb/trunk/
53 Added GET/PUT support through a FSL bus. sybreon 6115d 07h /aemb/trunk/
52 Added log output to iverilog.log sybreon 6115d 07h /aemb/trunk/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6116d 10h /aemb/trunk/
50 Parameterised optional components. sybreon 6116d 14h /aemb/trunk/
49 Added random seed for simulation. sybreon 6119d 17h /aemb/trunk/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6120d 23h /aemb/trunk/

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