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[/] [aemb/] [trunk/] [rtl/] - Rev 131

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Rev	Log message	Author	Age	Path
131	Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.	sybreon	5922d 02h	/aemb/trunk/rtl/
127	Fixed pipelined latching of data bug.	sybreon	5924d 13h	/aemb/trunk/rtl/
126	Fixed CMP bug.	sybreon	5924d 13h	/aemb/trunk/rtl/
125	Passes arithmetic tests with single thread.	sybreon	5926d 15h	/aemb/trunk/rtl/
124	FASM removed.	sybreon	5926d 15h	/aemb/trunk/rtl/
120	Basic version with some features left out.	sybreon	5927d 11h	/aemb/trunk/rtl/
119	Initial import.	sybreon	5927d 11h	/aemb/trunk/rtl/
118	Initial import.	sybreon	5930d 03h	/aemb/trunk/rtl/
114	changed MSR bits	sybreon	5936d 12h	/aemb/trunk/rtl/
105	Patch interrupt bug.	sybreon	6018d 03h	/aemb/trunk/rtl/
103	Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)	sybreon	6019d 12h	/aemb/trunk/rtl/
102	Fix MTS during interrupt vectoring bug (reported by M. Ettus).	sybreon	6019d 12h	/aemb/trunk/rtl/
101	Made multiplier pause with pipeline	sybreon	6029d 08h	/aemb/trunk/rtl/
100	multiplier issues	sybreon	6029d 08h	/aemb/trunk/rtl/
99	Minor cleanup	sybreon	6041d 03h	/aemb/trunk/rtl/
96	Stalls pipeline on MUL/BSF instructions results in minor speed improvements.	sybreon	6044d 05h	/aemb/trunk/rtl/
95	Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.	sybreon	6046d 07h	/aemb/trunk/rtl/
94	Prevent fHZD & rBRA[1]	sybreon	6048d 05h	/aemb/trunk/rtl/
93	Minor enable fix	sybreon	6048d 05h	/aemb/trunk/rtl/
92	Partitioned simulation model.	sybreon	6051d 09h	/aemb/trunk/rtl/

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[/] [aemb/] [trunk/] [rtl/] - Rev 131

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