URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 126

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
126	Fixed CMP bug.	sybreon	5898d 13h	/aemb/trunk/rtl/verilog/
125	Passes arithmetic tests with single thread.	sybreon	5900d 15h	/aemb/trunk/rtl/verilog/
124	FASM removed.	sybreon	5900d 15h	/aemb/trunk/rtl/verilog/
120	Basic version with some features left out.	sybreon	5901d 11h	/aemb/trunk/rtl/verilog/
119	Initial import.	sybreon	5901d 11h	/aemb/trunk/rtl/verilog/
118	Initial import.	sybreon	5904d 03h	/aemb/trunk/rtl/verilog/
114	changed MSR bits	sybreon	5910d 11h	/aemb/trunk/rtl/verilog/
105	Patch interrupt bug.	sybreon	5992d 02h	/aemb/trunk/rtl/verilog/
103	Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)	sybreon	5993d 11h	/aemb/trunk/rtl/verilog/
102	Fix MTS during interrupt vectoring bug (reported by M. Ettus).	sybreon	5993d 11h	/aemb/trunk/rtl/verilog/
101	Made multiplier pause with pipeline	sybreon	6003d 08h	/aemb/trunk/rtl/verilog/
100	multiplier issues	sybreon	6003d 08h	/aemb/trunk/rtl/verilog/
99	Minor cleanup	sybreon	6015d 03h	/aemb/trunk/rtl/verilog/
96	Stalls pipeline on MUL/BSF instructions results in minor speed improvements.	sybreon	6018d 05h	/aemb/trunk/rtl/verilog/
95	Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.	sybreon	6020d 07h	/aemb/trunk/rtl/verilog/
94	Prevent fHZD & rBRA[1]	sybreon	6022d 05h	/aemb/trunk/rtl/verilog/
93	Minor enable fix	sybreon	6022d 05h	/aemb/trunk/rtl/verilog/
92	Partitioned simulation model.	sybreon	6025d 08h	/aemb/trunk/rtl/verilog/
91	Made idle thread PC track main PC.	sybreon	6026d 14h	/aemb/trunk/rtl/verilog/
90	Fixed Carry bit bug.	sybreon	6026d 14h	/aemb/trunk/rtl/verilog/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 126

Filtering Options