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[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 134

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Rev Log message Author Age Path
134 Minor performance improvements. sybreon 5904d 15h /aemb/trunk/rtl/verilog/
132 Fixed minor typos. sybreon 5905d 08h /aemb/trunk/rtl/verilog/
131 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. sybreon 5905d 08h /aemb/trunk/rtl/verilog/
127 Fixed pipelined latching of data bug. sybreon 5907d 19h /aemb/trunk/rtl/verilog/
126 Fixed CMP bug. sybreon 5907d 19h /aemb/trunk/rtl/verilog/
125 Passes arithmetic tests with single thread. sybreon 5909d 21h /aemb/trunk/rtl/verilog/
124 FASM removed. sybreon 5909d 21h /aemb/trunk/rtl/verilog/
120 Basic version with some features left out. sybreon 5910d 16h /aemb/trunk/rtl/verilog/
119 Initial import. sybreon 5910d 16h /aemb/trunk/rtl/verilog/
118 Initial import. sybreon 5913d 09h /aemb/trunk/rtl/verilog/
114 changed MSR bits sybreon 5919d 17h /aemb/trunk/rtl/verilog/
105 Patch interrupt bug. sybreon 6001d 08h /aemb/trunk/rtl/verilog/
103 Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) sybreon 6002d 17h /aemb/trunk/rtl/verilog/
102 Fix MTS during interrupt vectoring bug (reported by M. Ettus). sybreon 6002d 17h /aemb/trunk/rtl/verilog/
101 Made multiplier pause with pipeline sybreon 6012d 14h /aemb/trunk/rtl/verilog/
100 multiplier issues sybreon 6012d 14h /aemb/trunk/rtl/verilog/
99 Minor cleanup sybreon 6024d 08h /aemb/trunk/rtl/verilog/
96 Stalls pipeline on MUL/BSF instructions results in minor speed improvements. sybreon 6027d 11h /aemb/trunk/rtl/verilog/
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6029d 12h /aemb/trunk/rtl/verilog/
94 Prevent fHZD & rBRA[1] sybreon 6031d 10h /aemb/trunk/rtl/verilog/

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