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[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 157

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Rev	Log message	Author	Age	Path
157	Added interrupt capability.	sybreon	5899d 23h	/aemb/trunk/rtl/verilog/
150	Optimisations.	sybreon	5902d 23h	/aemb/trunk/rtl/verilog/
149	Minor performance optimisation.	sybreon	5903d 07h	/aemb/trunk/rtl/verilog/
148	added iwb_tag_o signal tied to MSR_ICE.	sybreon	5903d 12h	/aemb/trunk/rtl/verilog/
147	Disconnect from pipeline.	sybreon	5903d 15h	/aemb/trunk/rtl/verilog/
140	Fixed minor typos.	sybreon	5903d 16h	/aemb/trunk/rtl/verilog/
134	Minor performance improvements.	sybreon	5904d 14h	/aemb/trunk/rtl/verilog/
132	Fixed minor typos.	sybreon	5905d 06h	/aemb/trunk/rtl/verilog/
131	Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.	sybreon	5905d 06h	/aemb/trunk/rtl/verilog/
127	Fixed pipelined latching of data bug.	sybreon	5907d 17h	/aemb/trunk/rtl/verilog/
126	Fixed CMP bug.	sybreon	5907d 17h	/aemb/trunk/rtl/verilog/
125	Passes arithmetic tests with single thread.	sybreon	5909d 19h	/aemb/trunk/rtl/verilog/
124	FASM removed.	sybreon	5909d 19h	/aemb/trunk/rtl/verilog/
120	Basic version with some features left out.	sybreon	5910d 15h	/aemb/trunk/rtl/verilog/
119	Initial import.	sybreon	5910d 15h	/aemb/trunk/rtl/verilog/
118	Initial import.	sybreon	5913d 07h	/aemb/trunk/rtl/verilog/
114	changed MSR bits	sybreon	5919d 16h	/aemb/trunk/rtl/verilog/
105	Patch interrupt bug.	sybreon	6001d 07h	/aemb/trunk/rtl/verilog/
103	Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)	sybreon	6002d 16h	/aemb/trunk/rtl/verilog/
102	Fix MTS during interrupt vectoring bug (reported by M. Ettus).	sybreon	6002d 16h	/aemb/trunk/rtl/verilog/

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[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 157

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