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[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 160

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Rev Log message Author Age Path
160 minor typo. sybreon 5994d 05h /aemb/trunk/rtl/verilog/
159 Backported Adder from AEMB2_EDK62.
Fixes 64-bit math problem reported by M. Ettus.		 sybreon 5994d 05h /aemb/trunk/rtl/verilog/
158 Got rid of the Greater-Than comparator.
Other minor size optimisations.		 sybreon 6004d 07h /aemb/trunk/rtl/verilog/
157 Added interrupt capability. sybreon 6004d 11h /aemb/trunk/rtl/verilog/
150 Optimisations. sybreon 6007d 11h /aemb/trunk/rtl/verilog/
149 Minor performance optimisation. sybreon 6007d 18h /aemb/trunk/rtl/verilog/
148 added iwb_tag_o signal tied to MSR_ICE. sybreon 6007d 23h /aemb/trunk/rtl/verilog/
147 Disconnect from pipeline. sybreon 6008d 02h /aemb/trunk/rtl/verilog/
140 Fixed minor typos. sybreon 6008d 03h /aemb/trunk/rtl/verilog/
134 Minor performance improvements. sybreon 6009d 01h /aemb/trunk/rtl/verilog/
132 Fixed minor typos. sybreon 6009d 18h /aemb/trunk/rtl/verilog/
131 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. sybreon 6009d 18h /aemb/trunk/rtl/verilog/
127 Fixed pipelined latching of data bug. sybreon 6012d 05h /aemb/trunk/rtl/verilog/
126 Fixed CMP bug. sybreon 6012d 05h /aemb/trunk/rtl/verilog/
125 Passes arithmetic tests with single thread. sybreon 6014d 07h /aemb/trunk/rtl/verilog/
124 FASM removed. sybreon 6014d 07h /aemb/trunk/rtl/verilog/
120 Basic version with some features left out. sybreon 6015d 03h /aemb/trunk/rtl/verilog/
119 Initial import. sybreon 6015d 03h /aemb/trunk/rtl/verilog/
118 Initial import. sybreon 6017d 19h /aemb/trunk/rtl/verilog/
114 changed MSR bits sybreon 6024d 03h /aemb/trunk/rtl/verilog/

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