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[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 186

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Rev Log message Author Age Path
186 added tool specific conditional defines. sybreon 5839d 18h /aemb/trunk/rtl/verilog/
172 single thread design sybreon 5879d 06h /aemb/trunk/rtl/verilog/
171 *** empty log message *** sybreon 5879d 18h /aemb/trunk/rtl/verilog/
170 initial sybreon 5879d 18h /aemb/trunk/rtl/verilog/
169 *** empty log message *** sybreon 5879d 18h /aemb/trunk/rtl/verilog/
168 *** empty log message *** sybreon 5879d 18h /aemb/trunk/rtl/verilog/
167 *** empty log message *** sybreon 5879d 18h /aemb/trunk/rtl/verilog/
166 final upload sybreon 5879d 19h /aemb/trunk/rtl/verilog/
160 minor typo. sybreon 5905d 02h /aemb/trunk/rtl/verilog/
159 Backported Adder from AEMB2_EDK62.
Fixes 64-bit math problem reported by M. Ettus.		 sybreon 5905d 02h /aemb/trunk/rtl/verilog/
158 Got rid of the Greater-Than comparator.
Other minor size optimisations.		 sybreon 5915d 03h /aemb/trunk/rtl/verilog/
157 Added interrupt capability. sybreon 5915d 07h /aemb/trunk/rtl/verilog/
150 Optimisations. sybreon 5918d 07h /aemb/trunk/rtl/verilog/
149 Minor performance optimisation. sybreon 5918d 14h /aemb/trunk/rtl/verilog/
148 added iwb_tag_o signal tied to MSR_ICE. sybreon 5918d 20h /aemb/trunk/rtl/verilog/
147 Disconnect from pipeline. sybreon 5918d 23h /aemb/trunk/rtl/verilog/
140 Fixed minor typos. sybreon 5918d 23h /aemb/trunk/rtl/verilog/
134 Minor performance improvements. sybreon 5919d 21h /aemb/trunk/rtl/verilog/
132 Fixed minor typos. sybreon 5920d 14h /aemb/trunk/rtl/verilog/
131 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. sybreon 5920d 14h /aemb/trunk/rtl/verilog/

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