URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 188

Rev	Log message	Author	Age	Path
188	* empty log message *	sybreon	5851d 23h	/aemb/trunk/rtl/verilog/
187	nc	sybreon	5866d 10h	/aemb/trunk/rtl/verilog/
186	added tool specific conditional defines.	sybreon	5866d 10h	/aemb/trunk/rtl/verilog/
172	single thread design	sybreon	5905d 22h	/aemb/trunk/rtl/verilog/
171	* empty log message *	sybreon	5906d 10h	/aemb/trunk/rtl/verilog/
170	initial	sybreon	5906d 10h	/aemb/trunk/rtl/verilog/
169	* empty log message *	sybreon	5906d 11h	/aemb/trunk/rtl/verilog/
168	* empty log message *	sybreon	5906d 11h	/aemb/trunk/rtl/verilog/
167	* empty log message *	sybreon	5906d 11h	/aemb/trunk/rtl/verilog/
166	final upload	sybreon	5906d 11h	/aemb/trunk/rtl/verilog/
160	minor typo.	sybreon	5931d 18h	/aemb/trunk/rtl/verilog/
159	Backported Adder from AEMB2_EDK62. Fixes 64-bit math problem reported by M. Ettus.	sybreon	5931d 18h	/aemb/trunk/rtl/verilog/
158	Got rid of the Greater-Than comparator. Other minor size optimisations.	sybreon	5941d 20h	/aemb/trunk/rtl/verilog/
157	Added interrupt capability.	sybreon	5941d 23h	/aemb/trunk/rtl/verilog/
150	Optimisations.	sybreon	5944d 23h	/aemb/trunk/rtl/verilog/
149	Minor performance optimisation.	sybreon	5945d 07h	/aemb/trunk/rtl/verilog/
148	added iwb_tag_o signal tied to MSR_ICE.	sybreon	5945d 12h	/aemb/trunk/rtl/verilog/
147	Disconnect from pipeline.	sybreon	5945d 15h	/aemb/trunk/rtl/verilog/
140	Fixed minor typos.	sybreon	5945d 16h	/aemb/trunk/rtl/verilog/
134	Minor performance improvements.	sybreon	5946d 14h	/aemb/trunk/rtl/verilog/