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[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 71

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Rev Log message Author Age Path
71 Old version deprecated. sybreon 6138d 06h /aemb/trunk/rtl/verilog/
70 Change interrupt to positive level triggered interrupts. sybreon 6139d 04h /aemb/trunk/rtl/verilog/
66 Added fsl_tag_o to FSL bus (tag either address or data). sybreon 6144d 22h /aemb/trunk/rtl/verilog/
65 Fixed minor typo causing synthesis failure. sybreon 6146d 10h /aemb/trunk/rtl/verilog/
63 Fixed interrupt signal synchronisation. sybreon 6146d 20h /aemb/trunk/rtl/verilog/
62 Fixed minor typo. sybreon 6146d 20h /aemb/trunk/rtl/verilog/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6146d 21h /aemb/trunk/rtl/verilog/
56 Parameterised optional components into aeMB_xecu.v sybreon 6150d 19h /aemb/trunk/rtl/verilog/
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6151d 03h /aemb/trunk/rtl/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6151d 23h /aemb/trunk/rtl/verilog/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6153d 02h /aemb/trunk/rtl/verilog/
50 Parameterised optional components. sybreon 6153d 05h /aemb/trunk/rtl/verilog/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6157d 14h /aemb/trunk/rtl/verilog/
45 Minor code cleanup. sybreon 6158d 11h /aemb/trunk/rtl/verilog/
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6159d 00h /aemb/trunk/rtl/verilog/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6159d 16h /aemb/trunk/rtl/verilog/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6170d 00h /aemb/trunk/rtl/verilog/
38 Added interrupt support. sybreon 6315d 01h /aemb/trunk/rtl/verilog/
36 Removed asynchronous reset signal. sybreon 6328d 11h /aemb/trunk/rtl/verilog/
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6329d 07h /aemb/trunk/rtl/verilog/

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