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[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 85

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Rev	Log message	Author	Age	Path
85	Replaced OF/ID blocks with combined block.	sybreon	6053d 03h	/aemb/trunk/rtl/verilog/
84	Added interrupt support.	sybreon	6053d 03h	/aemb/trunk/rtl/verilog/
83	Combined ID/OF blocks.	sybreon	6053d 03h	/aemb/trunk/rtl/verilog/
82	Further optimisations (speed + size).	sybreon	6055d 09h	/aemb/trunk/rtl/verilog/
81	Code cleanup + minor speed regression.	sybreon	6055d 10h	/aemb/trunk/rtl/verilog/
80	Minor optimisations (~10% faster)	sybreon	6056d 11h	/aemb/trunk/rtl/verilog/
78	initial import	sybreon	6058d 05h	/aemb/trunk/rtl/verilog/
76	initial	sybreon	6061d 11h	/aemb/trunk/rtl/verilog/
73	Moved simulation kernel into code.	sybreon	6068d 13h	/aemb/trunk/rtl/verilog/
72	Minor code cleanup.	sybreon	6068d 13h	/aemb/trunk/rtl/verilog/
71	Old version deprecated.	sybreon	6075d 16h	/aemb/trunk/rtl/verilog/
70	Change interrupt to positive level triggered interrupts.	sybreon	6076d 15h	/aemb/trunk/rtl/verilog/
66	Added fsl_tag_o to FSL bus (tag either address or data).	sybreon	6082d 08h	/aemb/trunk/rtl/verilog/
65	Fixed minor typo causing synthesis failure.	sybreon	6083d 21h	/aemb/trunk/rtl/verilog/
63	Fixed interrupt signal synchronisation.	sybreon	6084d 06h	/aemb/trunk/rtl/verilog/
62	Fixed minor typo.	sybreon	6084d 07h	/aemb/trunk/rtl/verilog/
61	Changed interrupt handling system (reported by M. Ettus).	sybreon	6084d 08h	/aemb/trunk/rtl/verilog/
56	Parameterised optional components into aeMB_xecu.v	sybreon	6088d 06h	/aemb/trunk/rtl/verilog/
55	Upgraded license to LGPLv3. Significant performance optimisations.	sybreon	6088d 13h	/aemb/trunk/rtl/verilog/
53	Added GET/PUT support through a FSL bus.	sybreon	6089d 09h	/aemb/trunk/rtl/verilog/

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[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 85

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