URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog/] - Rev 90

Rev	Log message	Author	Age	Path
90	Fixed Carry bit bug.	sybreon	6077d 21h	/aemb/trunk/rtl/verilog/
89	Changed simulation kernel.	sybreon	6077d 21h	/aemb/trunk/rtl/verilog/
88	Minor optimisations.	sybreon	6078d 13h	/aemb/trunk/rtl/verilog/
86	Some optimisations.	sybreon	6079d 07h	/aemb/trunk/rtl/verilog/
85	Replaced OF/ID blocks with combined block.	sybreon	6079d 07h	/aemb/trunk/rtl/verilog/
84	Added interrupt support.	sybreon	6079d 07h	/aemb/trunk/rtl/verilog/
83	Combined ID/OF blocks.	sybreon	6079d 07h	/aemb/trunk/rtl/verilog/
82	Further optimisations (speed + size).	sybreon	6081d 13h	/aemb/trunk/rtl/verilog/
81	Code cleanup + minor speed regression.	sybreon	6081d 14h	/aemb/trunk/rtl/verilog/
80	Minor optimisations (~10% faster)	sybreon	6082d 15h	/aemb/trunk/rtl/verilog/
78	initial import	sybreon	6084d 09h	/aemb/trunk/rtl/verilog/
76	initial	sybreon	6087d 15h	/aemb/trunk/rtl/verilog/
73	Moved simulation kernel into code.	sybreon	6094d 17h	/aemb/trunk/rtl/verilog/
72	Minor code cleanup.	sybreon	6094d 17h	/aemb/trunk/rtl/verilog/
71	Old version deprecated.	sybreon	6101d 20h	/aemb/trunk/rtl/verilog/
70	Change interrupt to positive level triggered interrupts.	sybreon	6102d 19h	/aemb/trunk/rtl/verilog/
66	Added fsl_tag_o to FSL bus (tag either address or data).	sybreon	6108d 12h	/aemb/trunk/rtl/verilog/
65	Fixed minor typo causing synthesis failure.	sybreon	6110d 01h	/aemb/trunk/rtl/verilog/
63	Fixed interrupt signal synchronisation.	sybreon	6110d 10h	/aemb/trunk/rtl/verilog/
62	Fixed minor typo.	sybreon	6110d 11h	/aemb/trunk/rtl/verilog/