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[/] [aemb/] [trunk/] [sim/] - Rev 144

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Rev Log message Author Age Path
144 Added VCD2LXT functions. sybreon 5950d 00h /aemb/trunk/sim/
143 Fixed minor typos. sybreon 5950d 00h /aemb/trunk/sim/
138 initial import sybreon 5950d 22h /aemb/trunk/sim/
98 Minor typo sybreon 6070d 18h /aemb/trunk/sim/
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6075d 19h /aemb/trunk/sim/
92 Partitioned simulation model. sybreon 6080d 21h /aemb/trunk/sim/
79 Modified for AEMB2 sybreon 6088d 15h /aemb/trunk/sim/
73 Moved simulation kernel into code. sybreon 6098d 23h /aemb/trunk/sim/
71 Old version deprecated. sybreon 6106d 02h /aemb/trunk/sim/
69 Removed unnecessary byte acrobatics with VMEM data. sybreon 6108d 21h /aemb/trunk/sim/
67 Minor simulation fixes. sybreon 6110d 20h /aemb/trunk/sim/
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6114d 18h /aemb/trunk/sim/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6115d 16h /aemb/trunk/sim/
53 Added GET/PUT support through a FSL bus. sybreon 6119d 19h /aemb/trunk/sim/
52 Added log output to iverilog.log sybreon 6119d 19h /aemb/trunk/sim/
50 Parameterised optional components. sybreon 6121d 02h /aemb/trunk/sim/
49 Added random seed for simulation. sybreon 6124d 05h /aemb/trunk/sim/
43 Added interrupt simulation.
Changed "human readable" simulation output.		 sybreon 6126d 21h /aemb/trunk/sim/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6127d 13h /aemb/trunk/sim/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6137d 21h /aemb/trunk/sim/

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