URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sim/] - Rev 200

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5584d 07h	/aemb/trunk/sim/
164	added random seed	sybreon	5867d 12h	/trunk/sim/
163	updated to new iversim compatibility	sybreon	5867d 12h	/trunk/sim/
162	Modified script to use verilog pre-processing. Changed /bin/bash to /bin/sh as suggested by "Wojciech A. Koszek" <wkoszek@freebsd.org> for FreeBSD compatibility.	sybreon	5870d 07h	/trunk/sim/
157	Added interrupt capability.	sybreon	5896d 17h	/trunk/sim/
156	initial import	sybreon	5896d 17h	/trunk/sim/
155	Minor cosmetic changes.	sybreon	5896d 17h	/trunk/sim/
144	Added VCD2LXT functions.	sybreon	5900d 10h	/trunk/sim/
143	Fixed minor typos.	sybreon	5900d 10h	/trunk/sim/
138	initial import	sybreon	5901d 08h	/trunk/sim/
98	Minor typo	sybreon	6021d 04h	/trunk/sim/
95	Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.	sybreon	6026d 05h	/trunk/sim/
92	Partitioned simulation model.	sybreon	6031d 07h	/trunk/sim/
79	Modified for AEMB2	sybreon	6039d 01h	/trunk/sim/
73	Moved simulation kernel into code.	sybreon	6049d 09h	/trunk/sim/
71	Old version deprecated.	sybreon	6056d 12h	/trunk/sim/
69	Removed unnecessary byte acrobatics with VMEM data.	sybreon	6059d 07h	/trunk/sim/
67	Minor simulation fixes.	sybreon	6061d 06h	/trunk/sim/
59	Added posedge/negedge bus interface. Modified interrupt test system.	sybreon	6065d 04h	/trunk/sim/
58	Updated simulation to also check BRI 0x00 instruction.	sybreon	6066d 02h	/trunk/sim/