URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sim/] - Rev 58

Rev	Log message	Author	Age	Path
58	Updated simulation to also check BRI 0x00 instruction.	sybreon	6179d 12h	/aemb/trunk/sim/
53	Added GET/PUT support through a FSL bus.	sybreon	6183d 15h	/aemb/trunk/sim/
52	Added log output to iverilog.log	sybreon	6183d 15h	/aemb/trunk/sim/
50	Parameterised optional components.	sybreon	6184d 21h	/aemb/trunk/sim/
49	Added random seed for simulation.	sybreon	6188d 01h	/aemb/trunk/sim/
43	Added interrupt simulation. Changed "human readable" simulation output.	sybreon	6190d 16h	/aemb/trunk/sim/
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6191d 08h	/aemb/trunk/sim/
39	Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.	sybreon	6201d 16h	/aemb/trunk/sim/
38	Added interrupt support.	sybreon	6346d 17h	/aemb/trunk/sim/
31	Removed byte acrobatics.	sybreon	6376d 20h	/aemb/trunk/sim/
30	Minor updates as sw/c/aeMB_testbench.c got updated.	sybreon	6379d 20h	/aemb/trunk/sim/
22	Added support for 8-bit and 16-bit data types.	sybreon	6381d 13h	/aemb/trunk/sim/
19	Added initial unified memory core.	sybreon	6393d 23h	/aemb/trunk/sim/
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6394d 15h	/aemb/trunk/sim/
15	Removed ROM file. Please generate it from the SW directory.	sybreon	6402d 21h	/aemb/trunk/sim/
13	Fibonacci rom	sybreon	6403d 05h	/aemb/trunk/sim/
2	initial import	sybreon	6428d 18h	/aemb/trunk/sim/