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[/] [aemb/] [trunk/] [sim/] - Rev 67

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Rev Log message Author Age Path
67 Minor simulation fixes. sybreon 6176d 12h /aemb/trunk/sim/
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6180d 10h /aemb/trunk/sim/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6181d 08h /aemb/trunk/sim/
53 Added GET/PUT support through a FSL bus. sybreon 6185d 11h /aemb/trunk/sim/
52 Added log output to iverilog.log sybreon 6185d 11h /aemb/trunk/sim/
50 Parameterised optional components. sybreon 6186d 17h /aemb/trunk/sim/
49 Added random seed for simulation. sybreon 6189d 21h /aemb/trunk/sim/
43 Added interrupt simulation.
Changed "human readable" simulation output.		 sybreon 6192d 13h /aemb/trunk/sim/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6193d 04h /aemb/trunk/sim/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6203d 13h /aemb/trunk/sim/
38 Added interrupt support. sybreon 6348d 13h /aemb/trunk/sim/
31 Removed byte acrobatics. sybreon 6378d 16h /aemb/trunk/sim/
30 Minor updates as sw/c/aeMB_testbench.c got updated. sybreon 6381d 16h /aemb/trunk/sim/
22 Added support for 8-bit and 16-bit data types. sybreon 6383d 10h /aemb/trunk/sim/
19 Added initial unified memory core. sybreon 6395d 19h /aemb/trunk/sim/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6396d 11h /aemb/trunk/sim/
15 Removed ROM file. Please generate it from the SW directory. sybreon 6404d 18h /aemb/trunk/sim/
13 Fibonacci rom sybreon 6405d 01h /aemb/trunk/sim/
2 initial import sybreon 6430d 14h /aemb/trunk/sim/

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