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[/] [aemb/] [trunk/] [sim/] [verilog/] - Rev 164

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Rev Log message Author Age Path
164 added random seed sybreon 5902d 07h /aemb/trunk/sim/verilog/
163 updated to new iversim compatibility sybreon 5902d 07h /aemb/trunk/sim/verilog/
157 Added interrupt capability. sybreon 5931d 12h /aemb/trunk/sim/verilog/
143 Fixed minor typos. sybreon 5935d 04h /aemb/trunk/sim/verilog/
138 initial import sybreon 5936d 03h /aemb/trunk/sim/verilog/
98 Minor typo sybreon 6055d 23h /aemb/trunk/sim/verilog/
95 Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. sybreon 6061d 00h /aemb/trunk/sim/verilog/
92 Partitioned simulation model. sybreon 6066d 02h /aemb/trunk/sim/verilog/
79 Modified for AEMB2 sybreon 6073d 20h /aemb/trunk/sim/verilog/
73 Moved simulation kernel into code. sybreon 6084d 04h /aemb/trunk/sim/verilog/
71 Old version deprecated. sybreon 6091d 07h /aemb/trunk/sim/verilog/
69 Removed unnecessary byte acrobatics with VMEM data. sybreon 6094d 02h /aemb/trunk/sim/verilog/
67 Minor simulation fixes. sybreon 6096d 01h /aemb/trunk/sim/verilog/
59 Added posedge/negedge bus interface.
Modified interrupt test system.		 sybreon 6099d 22h /aemb/trunk/sim/verilog/
58 Updated simulation to also check BRI 0x00 instruction. sybreon 6100d 21h /aemb/trunk/sim/verilog/
53 Added GET/PUT support through a FSL bus. sybreon 6105d 00h /aemb/trunk/sim/verilog/
50 Parameterised optional components. sybreon 6106d 06h /aemb/trunk/sim/verilog/
49 Added random seed for simulation. sybreon 6109d 10h /aemb/trunk/sim/verilog/
43 Added interrupt simulation.
Changed "human readable" simulation output.		 sybreon 6112d 01h /aemb/trunk/sim/verilog/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6112d 17h /aemb/trunk/sim/verilog/

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