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[/] [aemb/] [trunk/] [sim/] [verilog/] - Rev 202

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Rev	Log message	Author	Age	Path
191	New directory structure.	root	5586d 12h	/aemb/trunk/sim/verilog/
164	added random seed	sybreon	5869d 16h	/aemb/trunk/sim/verilog/
163	updated to new iversim compatibility	sybreon	5869d 16h	/aemb/trunk/sim/verilog/
157	Added interrupt capability.	sybreon	5898d 22h	/aemb/trunk/sim/verilog/
143	Fixed minor typos.	sybreon	5902d 14h	/aemb/trunk/sim/verilog/
138	initial import	sybreon	5903d 12h	/aemb/trunk/sim/verilog/
98	Minor typo	sybreon	6023d 09h	/aemb/trunk/sim/verilog/
95	Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.	sybreon	6028d 10h	/aemb/trunk/sim/verilog/
92	Partitioned simulation model.	sybreon	6033d 12h	/aemb/trunk/sim/verilog/
79	Modified for AEMB2	sybreon	6041d 06h	/aemb/trunk/sim/verilog/
73	Moved simulation kernel into code.	sybreon	6051d 13h	/aemb/trunk/sim/verilog/
71	Old version deprecated.	sybreon	6058d 16h	/aemb/trunk/sim/verilog/
69	Removed unnecessary byte acrobatics with VMEM data.	sybreon	6061d 12h	/aemb/trunk/sim/verilog/
67	Minor simulation fixes.	sybreon	6063d 11h	/aemb/trunk/sim/verilog/
59	Added posedge/negedge bus interface. Modified interrupt test system.	sybreon	6067d 08h	/aemb/trunk/sim/verilog/
58	Updated simulation to also check BRI 0x00 instruction.	sybreon	6068d 07h	/aemb/trunk/sim/verilog/
53	Added GET/PUT support through a FSL bus.	sybreon	6072d 10h	/aemb/trunk/sim/verilog/
50	Parameterised optional components.	sybreon	6073d 16h	/aemb/trunk/sim/verilog/
49	Added random seed for simulation.	sybreon	6076d 19h	/aemb/trunk/sim/verilog/
43	Added interrupt simulation. Changed "human readable" simulation output.	sybreon	6079d 11h	/aemb/trunk/sim/verilog/

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[/] [aemb/] [trunk/] [sim/] [verilog/] - Rev 202

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