URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sim/] [verilog/] - Rev 205

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5661d 20h	/aemb/trunk/sim/verilog/
164	added random seed	sybreon	5945d 00h	/aemb/trunk/sim/verilog/
163	updated to new iversim compatibility	sybreon	5945d 00h	/aemb/trunk/sim/verilog/
157	Added interrupt capability.	sybreon	5974d 06h	/aemb/trunk/sim/verilog/
143	Fixed minor typos.	sybreon	5977d 22h	/aemb/trunk/sim/verilog/
138	initial import	sybreon	5978d 20h	/aemb/trunk/sim/verilog/
98	Minor typo	sybreon	6098d 17h	/aemb/trunk/sim/verilog/
95	Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.	sybreon	6103d 18h	/aemb/trunk/sim/verilog/
92	Partitioned simulation model.	sybreon	6108d 20h	/aemb/trunk/sim/verilog/
79	Modified for AEMB2	sybreon	6116d 14h	/aemb/trunk/sim/verilog/
73	Moved simulation kernel into code.	sybreon	6126d 21h	/aemb/trunk/sim/verilog/
71	Old version deprecated.	sybreon	6134d 00h	/aemb/trunk/sim/verilog/
69	Removed unnecessary byte acrobatics with VMEM data.	sybreon	6136d 20h	/aemb/trunk/sim/verilog/
67	Minor simulation fixes.	sybreon	6138d 19h	/aemb/trunk/sim/verilog/
59	Added posedge/negedge bus interface. Modified interrupt test system.	sybreon	6142d 16h	/aemb/trunk/sim/verilog/
58	Updated simulation to also check BRI 0x00 instruction.	sybreon	6143d 15h	/aemb/trunk/sim/verilog/
53	Added GET/PUT support through a FSL bus.	sybreon	6147d 18h	/aemb/trunk/sim/verilog/
50	Parameterised optional components.	sybreon	6149d 00h	/aemb/trunk/sim/verilog/
49	Added random seed for simulation.	sybreon	6152d 03h	/aemb/trunk/sim/verilog/
43	Added interrupt simulation. Changed "human readable" simulation output.	sybreon	6154d 19h	/aemb/trunk/sim/verilog/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sim/] [verilog/] - Rev 205

Filtering Options